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HM-6516
March 1997
2K x 8 CMOS RAM
Description
The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques that keep the active (operating) power low, which also gives fast access times. The pinout of the HM-6516 is the popular 24 pin, 8-bit wide JEDEC standard, which allows easy memory board layouts, flexible enough to accommodate a variety of PROMs, RAMS, EPROMs, and ROMs. The HM-6516 is ideally suited for use in microprocessor based systems. The byte wide organization simplifies the memory array design, and keeps operating power down to a minimum, because only one device is enabled at a time. The address latches allow very simple interfacing to recent generation microprocessors which employ a multiplexed address/data bus. The convenient output enable control also simplifies multiplexed bus interfacing by allowing the data outputs to be controlled independent of the chip enable.
Features
* Low Power Standby . . . . . . . . . . . . . . . . . . . 275W Max * Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max * Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max * Industry Standard Pinout * Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC * TTL Compatible * Static Memory Cells * High Output Drive * On-Chip Address Latches * Easy Microprocessor Interfacing
Ordering Information
120ns HM1-6516B-9 8403607JA 8403607ZA 200ns HM1-6516-9 29102BJA 8403601JA HM4-6516-9 8403601ZA TEMP. RANGE -40oC to +85oC -55oC to +125oC -55oC to +125oC -40oC to +85oC -55oC to +125oC PACKAGE CERDIP JAN# SMD# CLCC SMD# F24.6 F24.6 F24.6 J32.A J32.A PKG. NO.
Pinouts
HM-6516 (CERDIP) TOP VIEW
NC A7
HM-6516 (CLCC) TOP VIEW
NC NC VCC NC NC
PIN
29 A8 28 A9 27 NC 26 W 25 G 24 A10 23 E 22 DQ7 21 DQ6
DESCRIPTION No Connect Address Inputs Chip Enable/Power Down Ground
A7 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 DQ0 9 DQ1 10 DQ2 11 GND 12
24 VCC 23 A8 22 A9 21 W 20 G 19 A10 18 E 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3
4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 DQ0 13
3
2
1
32 31 30
NC A0 - A10 E VSS/GND
DQ0 - DQ7 Data In/Data Out VCC W G Power (+5V) Write Enable Output Enable
14 15 16 17 18 19 20 GND DQ1 DQ2 DQ3 DQ4 DQ5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2998.1
6-1
HM-6516 Functional Diagram
A10 A9 A8 A7 A6 A5 A4
A 7 LATCHED ADDRESS REGISTER A 7 L G G 16 16 16 16 16 16 16 16 A 8 A 4 A A L 4 8 DQ0 THRU DQ7 1 OF 8 GATED ROW DECODER 128 x 128 MATRIX
128
G
GATED COLUMN DECODER
W
E
LATCHED ADDRESS REGISTER
A3
A2
A1
A0
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HM-6516
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Ranges: HM-6516B-9, HM-6516-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9) LIMITS
SYMBOL ICCSB
PARAMETER Standby Supply Current
MIN -
MAX 50
UNITS A A mA A A V A A V V V V V
TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V, HM-6516B-9 IO = 0mA, VI = VCC or GND, HM-6516-9 f = 1MHz, IO = 0mA, G = VCC, VCC = 5.5V, VI = VCC or GND VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC, HM-6516B-9 VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC, HM-6516-9
-
100
ICCOP
Operating Supply Current (Note 1)
-
10
ICCDR
Data Retention Supply Current
-
25
-
50
VCCDR II IIOZ VIL VIH VOL VOH1 VOH2
Data Retention Supply Voltage Input Leakage Current Input/Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
2.0 -1.0 -1.0 -0.3 2.4 2.4 VCC -0.4
+1.0 +1.0 0.8 VCC +0.3 0.4 -
VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 3.2mA, VCC = 4.5V IO = -1.0mA, VCC = 4.5V IO = -100A, VCC = 4.5V
Capacitance
SYMBOL CI CIO NOTES:
MAX 8 10
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
6-3
HM-6516
AC Electrical Specifications VCC = 5V 10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)
LIMITS HM-6516B-9 SYMBOL
(1) TELQV (2) TAVQV (3) TELQX (4) TWLQZ (5) TEHQZ (6) TGLQV (7) TGLQX (8) TGHQZ (9) TELEH (10) TEHEL (11) TAVEL (12) TELAX (13) TWLWH (14) TWLEH (15) TELWH (16) TDVWH (17) TWHDX (18) TELEL
HM-6516-9 MIN 10 10 200 80 0 50 200 200 200 80 10 280 MAX 200 200 80 80 80 80 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
PARAMETER Chip Enable Access Time Address Access Time Chip Enable Output Enable Time Write Enable Output Disable Time Chip Enable Output Disable Time Output Enable Output Valid Time Output Enable Output Enable Time Output Enable Output DisableTime Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Write Enable Pulse Width Write Enable Pulse Setup Time Write Enable Pulse Hold Time Data Setup Time Data Hold Time Read or Write Cycle Time
MIN 10 10 120 50 0 30 120 120 120 50 10 170
MAX 120 120 50 50 80 50 -
NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL.
6-4
HM-6516 Timing Waveforms
(2) TAVQV (12) TELAX (11) A (10) TEHEL E HIGH W (5) TEHQZ (1) TELQV (5) TEHQZ TAVEL VALID ADD (18) TELEL (11) TAVEL NEXT ADD
(9) TELEH
(10) TEHEL
(3) TELQX
DQ (6) TGLQV G (7) TGLQX TIME REFERENCE -1 0 1
VALID DATA OUT TGHQZ (8)
2
3
4
5
FIGURE 1. READ CYCLE
The address information is latched in the on-chip registers on the falling edge of E (T = 0), minimum address setup and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1), the outputs become enabled but data is not valid until time (T = 2), W must
remain high throughout the read cycle. After the data has been read, E may return high (T = 3). This will force the output buffers into a high impedance mode at time (T = 4). G is used to disable the output buffers when in a logical "1" state (T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for the next cycle.
Timing Waveforms (Continued)
(11) TAVEL A (12) TELAX (11) TAVEL NEXT ADD (18) TELEL
VALID ADD
(10) TEHEL E
(9) TELEH
(10) TEHEL
(14) TWLEH (13) TWLWH W (15) TELWH (16) TDVWH VALID DATA IN HIGH (17) TWHDX
DQ G TIME REFERENCE -1 0 1
2
3
4
5
FIGURE 2. WRITE CYCLE
6-5
HM-6516
The write cycle is initiated on the falling edge of E (T = 0), which latches the address information in the on-chip registers. If a write cycle is to be performed where the output is not to become active, G can be held high (inactive). TDVWH and TWHDX must be met for proper device operation regardless of G. If E and G fall before W falls (read mode), a possible bus conflict may exist. If E rises before W rises, reference data setup and hold times to the E rising edge. The write operation is terminated by the first rising edge of W (T = 2) or E (T = 3). After the minimum E high time (TEHEL), the next cycle may begin. If a series of consecutive write cycles are to be performed, the W line may be held low until all desired locations have been written. In this case, data setup and hold times must be referenced to the rising of E.
Typical Performance Curve
-3 -4 -5 LOG (ICC/(1A)) -6 -7 -8 -9 -10 -11 -12 -55 VCC = 2.0V
-35
-15
5
25
45
65
85
105
125
FIGURE 3. TYPICAL ICCDR vs TA
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
6-6
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